ISBN: 9780262319096 | 352 pp. | December 2013

Finite State Machines in Hardware

Theory and Design (with VHDL and SystemVerilog)

Modern, complex digital systems invariably include hardware-implemented finite state machines. The correct design of such parts is crucial for attaining proper system performance. This book offers detailed, comprehensive coverage of the theory and design for any category of hardware-implemented finite state machines. It describes crucial design problems that lead to incorrect or far from optimal implementation and provides examples of finite state machines developed in both VHDL and SystemVerilog (the successor of Verilog) hardware description languages.

Important features include: extensive review of design practices for sequential digital circuits; a new division of all state machines into three hardware-based categories, encompassing all possible situations, with numerous practical examples provided in all three categories; the presentation of complete designs, with detailed VHDL and SystemVerilog codes, comments, and simulation results, all tested in FPGA devices; and exercise examples, all of which can be synthesized, simulated, and physically implemented in FPGA boards. Additional material is available on the book's Website.

Designing a state machine in hardware is more complex than designing it in software. Although interest in hardware for finite state machines has grown dramatically in recent years, there is no comprehensive treatment of the subject. This book offers the most detailed coverage of finite state machines available. It will be essential for industrial designers of digital systems and for students of electrical engineering and computer science.

Table of Contents

  1. Preface
  2. Acknowledgments
  3. 1. The Finite State Machine Approach
  4. 2. Hardware Fundamentals—Part I
  5. 3. Hardware Fundamentals—Part II
  6. 4. Design Steps and Classical Mistakes
  7. 5. Regular (Category 1) State Machines
  8. 6. VHDL Design of Regular (Category 1) State Machines
  9. 7. SystemVerilog Design of Regular (Category 1) State Machines
  10. 8. Timed (Category 2) State Machines
  11. 9. VHDL Design of Timed (Category 2) State Machines
  12. 10. DSystemVerilog Design of Timed (Category 2) State Machines
  13. 11. Recursive (Category 3) State Machines
  14. 12. VHDL Design of Recursive (Category 3) State Machines
  15. 13. SystemVerilog Design of Recursive (Category 3) State Machines
  16. 14. Additional Design Examples
  17. 15. Pointer-Based FSM Implementation
  18. Bibliography
  19. Index